1. Field of the Invention
This invention relates to digital computer memory systems and other data processing systems.
The invention further relates to a unidirectional or looped bus architecture for transmitting data, instructions and other information between a central processing unit and a plurality of storage and input/output devices.
2. Description of the Prior Art
State of the art microprocessor designs provide three or four basic and separate functional components. First is the ROS (sometimes RAM) microinstruction address register with its incrementing, branching and linking hardware. Second is the central arithmetic and logic unit (ALU) with its associated registers and data paths. Third is the addressing and data interconnection with the main storage, that is usually treated as input/output (I/O) unit, and is architecturally combined with other system I/O devices. If the microprocessor is sophisticated enough, it will also include a fourth separate section of registers and data paths, usually defined as a channel, for performing priority nested interrupts switching, and optionally, priority multiplexed or burst mode cycle steal control (sometimes referred to as direct memory access, or DMA.)
Current microprocessors can be classified into two approaches that divide the above noted functions into a multi-chip set. The first approach allocates different functions to separate chips such as an ALU chip, a control chip, an address chip, an I/O chip, and ROS/RAM (sometimes with address control) storage chips. The second approach distributes processor functions through a number of identical chips: this approach is known as the "bit slice technique," and usually requires separate I/O control chips.
Either approach requires extensive chip interconnection, which is limited by the available I/O pins and, consequently results in duplication of logic, and also delays through the required off-chip drivers and receivers. If the data or address busses are bidirectional, no signals may be sent or received until an all off and then an all on control state is established between each chip's drivers and receivers; this causes additional delays. Also, each of these bidirectional busses require I/O pins and off chip drivers, resulting in a larger chip layout and, even worse, a higher chip power dissipation. To overcome this drawback, some architectures combine the address and data busses into one time multiplexed "Unibus," compounding further the controls and handshaking delays.
Consequently, a microprocessor architecture which minimizes the number of drivers and receivers and which can be packaged on a single chip having about 68 pin connections is needed to optimize cost and performance.